HD6417750 Datasheet, PDF (513/1039 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
/
D63–D0
Tm1 Tmd1w Tmd1 Tmd2 Tmd3 Tmd4
A
D0
D1
D2
D3
RD/
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.61 MPX Interface Timing 5
(Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits,
Transfer Data Size: 32 Bytes)
Rev. 6.0, 07/02, page 461 of 986