HD6417750 Datasheet, PDF (494/1039 Pages) Renesas Technology Corp – SuperH RISC engine

In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width.
The first access is performed on the data for which there was an access request, and the remaining
accesses are performed on the data at the 32-byte boundary. The bus is not released during this
period.
Figure 13.48 shows the timing when a burst ROM setting is made, and setup/hold is specified in
WCR3.
CKIO
A25–A5
T1 TB2 TB1 TB2 TB1 TB2 TB1 T2
A4–A0
RD/
D63–D0
(read)
DACKn
(SA: IO ← memory)
Notes: 1. For a write cycle, a basic bus cycle (write cycle) is performed.
2. For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.46 Burst ROM Basic Access Timing
Rev. 6.0, 07/02, page 442 of 986