HD6417750 Datasheet, PDF (444/1039 Pages) Renesas Technology Corp – SuperH RISC engine

SH7750 Series
A16
A0
D7
D0
128k × 8-bit
SRAM
A16
A0
I/O7
I/O0
Figure 13.10 Example of 8-Bit Data Width SRAM Connection
Wait State Control: Wait state insertion on the SRAM interface can be controlled by the WCR2
settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a
software wait is inserted in accordance with that specification. For details, see section 13.2.6, Wait
Control Register 2 (WCR2).
The specified number of Tw cycles are inserted as wait cycles using the SRAM interface wait
timing shown in figure 13.11.
Rev. 6.0, 07/02, page 392 of 986