HD6417750 Datasheet, PDF (624/1039 Pages) Renesas Technology Corp – SuperH RISC engine

c. In the SH7750S and SH7750R, initial settings can be made in the DMAC channel 0 control
register from the CPU (possible settings are CHCR0.RS = 0000, 0010, or 0011). If settings
of DTR.ID = 00, DTR.MD = 00, and DTR.SZ ≠ 101 or 110 are subsequently input, a
transfer request to channel 0 will be asserted.
4. Handshake protocol without use of the data bus
a. With the handshake protocol without use of the data bus, a DMA transfer request can be
input to the DMAC again for the channel for which transfer was requested immediately
before by asserting 75 only.
b. When using the handshake protocol without use of the data bus, first make the necessary
settings in the DMAC control registers.
c. When not using the handshake protocol without use of the data bus, if 75 only is asserted
without outputting DTR, a request will be issued for the channel for which DMA transfer
was requested immediately before. Also, if the first DMA transfer request after a power-on
reset is input by asserting 75 only, it will be ignored and the DMAC will not operate.
d. If 75 only is asserted by means of the handshake protocol without use of the data bus and a
DMA transfer request is input when channel 0 DMA transfer has ended and CHCR0.TE =
1, the DMAC will freeze. Before issuing a DMA transfer request, the TE flag must be
cleared by writing CHCR0.TE = 0 after reading CHCR0.TE = 1.
5. Direct data transfer mode (valid on channel 2 only)
a. If a DMA transfer request for channel 2 is input by simultaneous assertion of '%5(4 and
75 during DMA transfer execution with the handshake protocol without use of the data
bus, it will be accepted if there is space in the DDT channel 2 request queue.
b. In direct data transfer mode (with '%5(4 and 75 asserted simultaneously), '%5(4 is not
interpreted as a bus arbitration signal, and therefore the %$9/ signal is never asserted.
6. Request queue transfer request acceptance
a. The DDT has four request queues for each of channels 1 to 3. When these request queues
are full, a DMA transfer request from an external device will be ignored.
b. If a DMA transfer request for channel 0 is input during execution of a channel 0 DMA bus
cycle, the DDT will ignore that request. Confirm that channel 0 DMA transfer has finished
(burst mode) or that a DMA bus cycle is not in progress (cycle steal mode).
7. DTR format
a. The DDT module processes DTR.ID, DTR.MD, and DTR.SZ as follows.
When DTR.ID= 00
• MD = 00, SZ ≠ 101, 110: Handshake protocol using the data bus
• MD ≠ 00, SZ = 111: CHCR0.DE = 0 setting (DMA transfer end request)
• MD ≠ 10, SZ = 110: DDT request queue clear
When DTR.ID ≠ 00
• Transfer request to channels 1—3 (items other than ID ignored)
Rev. 6.0, 07/02, page 572 of 986