HD6417750 Datasheet, PDF (12/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Section
Page
13.1.4 Register Configuration 318
13.1.5 Overview of Areas 320
319
320
321, 322
13.2.1 Bus Control Register 326
1 (BCR1)
327
328
330
330
331
332
333
334
13.2.2 Bus Control Register 335
2 (BCR2)
13.2.3 Bus Control Register 337
3 (BCR3) (SH7750R Only) ₃₃₈
13.2.4 Bus Control Register 338,
4 (BCR4)
339
13.2.5 Wait Control Register 342
1 (WCR1)
13.2.6 Wait Control Register 344 to
2 (WCR2)
349
13.2.7 Wait Control Register 351
3 (WCR3)
351
Item
Description
Table 13.2 BSC Registers
Bus control register 3
and 4 added to table,
and Note added
Table 13.3 External Memory 64*⁷ added to Area 0, 5,
Space Map
6 Settable Bus Widths,
and Note 7 added
Space Divisions
Description amended
Table 13.3 External Memory Table amended, and
Space Map
Notes amended and
added
Memory Bus Width
Description added
Bit table
Bit 18 amended and
note added
Bit 31, Bit 30, Bit 29
Description added
Bit 26
Bit 16
Description and notes
added
Bit 15, Bit 14
Description amended
Bits 13 to 11
Bits 10 to 8
Table amended and
note added
Bits 7 to 5
Bit 0
Description amended
Bits 15, 14
Description added
Bits 12 to 1—Reserved
Newly added
Description added
Newly added
Note amended
Bits 31 to 29, Bits 25 to 23,
Bits 19 to 17, Bits 15 to 13,
Bits 11 to 9, Bits 8 to 6,
Bits 5 to 3, and Bits 2 to 0
Bit table
Description added and
amended
Bits 19 and 7 changed,
and Note added
Description added
Rev. 6.0, 07/02, page x of I