HD6417750 Datasheet, PDF (518/1039 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
/
D31–D0
Tm1
Tmd1w Tmd1w
Tmd1
Tmd2
A
D0
D1
RD/
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.66 MPX Interface Timing 2
(Burst Read Cycle, AnW = 0, One External Wait Inserted, Bus Width: 32 Bits,
Transfer Data Size: 64 Bytes)
Rev. 6.0, 07/02, page 466 of 986