HD6417750 Datasheet, PDF (727/1039 Pages) Renesas Technology Corp – SuperH RISC engine

The SCBRR2 setting is found from the following equation.
Asynchronous mode:
N=
Pφ
× 10⁶ – 1
64 × 2^2n–1 × B
Where B: Bit rate (bits/s)
N: SCBRR2 setting for baud rate generator (0 ≤ N ≤ 255)
Pφ: Peripheral module operating frequency (MHz)
n: Baud rate generator input clock (n = 0 to 3)
(See the table below for the relation between n and the clock.)
SCSMR2 Setting
n
Clock
CKS1
CKS0
0
Pφ
0
0
1
Pφ/4
0
1
2
Pφ/16
1
0
3
Pφ/64
1
1
The bit rate error in asynchronous mode is found from the following equation:
Error (%) =
P_φ × 10⁶
(N + 1) × B × 64 × 2^2n–1
–1
× 100
16.2.9 FIFO Control Register (SCFCR2)
Bit: 15
14
13
12
—
—
—
—
Initial value:
0
0
0
0
R/W: R
R
R
R
11
10
9
8
— RSTRG2* RSTRG1* RSTRG0*
0
0
0
0
R
R/W
R/W
R/W
Bit:
Initial value:
R/W:
7
RTRG1
0
R/W
6
RTRG0
0
R/W
5
TTRG1
0
R/W
4
TTRG0
0
R/W
Note: * Reserved bit in the SH7750.
3
MCE
0
R/W
2
TFRST
0
R/W
1
RFRST
0
R/W
0
LOOP
0
R/W
Rev. 6.0, 07/02, page 675 of 986