HD6417750 Datasheet, PDF (178/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Example 3: When an instruction that generates an exception does not branch using a branch instruction
Instruction 1 (branch instruction) ; Address of this instruction is saved to SPC when exception occurs.
Instruction 2 ; May be executed if an SQ store instruction.
Instruction 3 ; May be executed if an SQ store instruction.
Instruction 4 ; May be executed if an SQ store instruction.
Instruction 5
To recover from this problem it is necessary that conditions A and B be satisfied.
A: After the PREF instruction to transfer data from the store queue (SQ0, SQ1) to external
memory, a store instruction for the same store queue must be executed, and conditions (1) and
(2) below must be satisfied.
(1) Three NOP instructions*¹ must be inserted between the above two instructions.
(2) There must not be a PREF instruction to transfer data from the store queue to external
memory in the delay slot of the branch instruction.
B: There must be no PREF instruction to transfer data from the store queue to external memory
executed in the exception handling routine.
If such an instruction is executed, and if there is a store to the store queue instruction among
the four instructions*² at the address referred to by SPC, the data transferred to external
memory by the PREF instruction may indicate that execution of the store instruction has
completed.
Notes: *1 If there are other instructions between the above two instructions, the problem can be
avoided if the other instructions and NOP instructions together total three or more
instructions.
*2 If the instruction at the address referred to by SPC is a branch instruction the two
instructions at the branch destination may be affected.
Rev. 6.0, 07/02, page 126 of 986