HD6417750 Datasheet, PDF (186/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Pipeline flow:
Instruction n
Instruction n+1
TLB miss (data access)
IF ID EX MA WB
IF ID EX MA WB
General illegal instruction exception
Instruction n+2
TLB miss (instruction access)
IF ID EX MA WB
Instruction n+3
IF ID EX MA WB
Order of detection:
General illegal instruction exception (instruction n+1) and
TLB miss (instruction n+2) are detected simultaneously
IF: Instruction fetch
ID: Instruction decode
EX: Instruction execution
MA: Memory access
WB: Write-back
TLB miss (instruction n)
Order of exception handling:
TLB miss (instruction n)
Re-execution of instruction n
Program order
1
General illegal instruction exception
(instruction n+1)
2
Re-execution of instruction n+1
TLB miss (instruction n+2)
3
Re-execution of instruction n+2
Execution of instruction n+3
4
Figure 5.3 Example of General Exception Acceptance Order
Rev. 6.0, 07/02, page 134 of 986