HD6417750 Datasheet, PDF (792/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Table 18.2 shows the SCI I/O port pin configuration.
Table 18.2 SCI I/O Port Pins
Pin Name
Abbreviation
I/O
Function
Serial clock pin
MD0/SCK
I/O
Clock input/output
Receive data pin
RxD
Input
Receive data input
Transmit data pin
MD7/TxD
Output
Transmit data output
Note:
Pins MD0/SCK and MD7/TxD function as mode input pins MD0 and MD7 after a power-on
reset. They are made to function as serial pins by performing SCI operation settings with
the TE, RE, CKEI, and CKE0 bits in SCSCR1 and the C/$ bit in SCSMR1. Break state
transmission and detection can be performed by means of a setting in the SCI’s SCSPTR1
register.
Table 18.3 shows the SCIF I/O port pin configuration.
Table 18.3 SCIF I/O Port Pins
Pin Name
Abbreviation
I/O
Function
Serial clock pin
05(6(7/SCK2 Input
Clock input
Receive data pin
MD2/RxD2
Input
Receive data input
Transmit data pin
MD1/TxD2
Output
Transmit data output
Modem control pin &765
I/O
Transmission enabled
Modem control pin MD8/5765
I/O
Transmission request
Note:
The MRESET/SCK2 pin functions as the 05(6(7 manual reset pin when a manual reset is
executed. The MD1/TxD2, MD2/RxD2, and MD8/5765 pins function as the MD1, MD2, and
MD8 mode input pins after a power-on reset. These pins are made to function as serial pins
by performing SCIF operation settings with the TE and RE bits in SCSCR2 and the MCE bit
in SCFCR2. Break state transmission and detection can be set in the SCIF’s SCSPTR2
register.
Rev. 6.0, 07/02, page 740 of 986