HD6417750 Datasheet, PDF(469/1039 Page) Renesas Technology Corp – SuperH RISC engine

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HD6417750 Datasheet, PDF (469/1039 Pages) Renesas Technology Corp – SuperH RISC engine

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CKIO

Bank

Precharge-sel

Address

Tr

Trw

Tc1

Tc2

Tc3

Tc4/Td1

Td2

Td3

Td4

Row

Row

H/L

Row

c0

RD/

DQMn

D63âD0

(read)

d0

d1

d2

d3

CKE

DACKn

(SA: IO â memory)

Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.28 Basic Timing for Synchronous DRAM Burst Read

In a synchronous DRAM cycle, the %6 signal is asserted for one cycle at the start of the data

transfer cycle corresponding to the READ or READA command. The order of access is as

follows: in a fill operation in the event of a cache miss, 64-bit boundary data including the missed

data is read first, then 16-byte boundary data including the missed data is read in wraparound

mode. The remaining 16 bytes of the 32-byte boundary data are read by the READA command

issued next.

Rev. 6.0, 07/02, page 417 of 986

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