HD6417750 Datasheet, PDF (452/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Basic Timing: The basic timing for DRAM access is 4 cycles. This basic timing is shown in
figure 13.17. Tpc is the precharge cycle, Tr the 5$6 assert cycle, Tc1 the &$6 assert cycle, and
Tc2 the read data latch cycle.
CKIO
A25–A0
Tr1
Tr2
Tc1
Tc2
Tpc
Row
Column
RD/
D63–D0
(read)
D63–D0
(write)
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.17 Basic DRAM Access Timing
Rev. 6.0, 07/02, page 400 of 986