HD6417750 Datasheet, PDF (631/1039 Pages) Renesas Technology Corp – SuperH RISC engine

14.7 Register Descriptions (SH7750R)
14.7.1 DMA Source Address Registers 0–7 (SAR0–SAR7)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DMA source address registers 0–7 (SAR0–SAR7) are 32-bit readable/writable registers that
specify the source address for a DMA transfer. The functions of these registers are the same as on
the SH7750 or SH7750S. For more information, see section 14.2.1, DMA Source Address
Registers 0–3 (SAR0–SAR3).
14.7.2 DMA Destination Address Registers 0–7 (DAR0–DAR7)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DMA destination address registers 0–7 (DAR0–DAR7) are 32-bit readable/writable registers that
specify the destination address for a DMA transfer. The functions of these registers are the same
as on the SH7750 and SH7750S. For more information, see section 14.2.2, DMA Destination
Address Registers 0–3 (DAR0–DAR3).
Rev. 6.0, 07/02, page 579 of 986