HD6417750 Datasheet, PDF(415/1039 Page) Renesas Technology Corp – SuperH RISC engine

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HD6417750 Datasheet, PDF (415/1039 Pages) Renesas Technology Corp – SuperH RISC engine

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For example, to write H'0230 to the area 2 SDMR register, arbitrary data is written to address

H'FF900000 (address âYâ) + H'08C0 (value âXâ) (= H'FF9008C0). As a result, H'0230 is written

to the SDMR register. The range of value âXâ is H'0000 to H'0FFC.

Similarly, to write H'0230 to the area 3 SDMR register, arbitrary data is written to address

H'FF940000 (address âYâ) + H'08C0 (value âXâ) (= H'FF9408C0). As a result, H'0230 is written

to the SDMR register. The range of value âXâ is H'0000 to H'0FFC.

The lower 16 bits of the address are set in the synchronous DRAM mode register.

When the bus width is 32 bits, the burst length is 4* and 8. When the bus width is 64 bits, the burst

length is fixed at 4. When a setting is made in SDMR, byte-size writes are performed at the

following addresses.

Bus Width

32

32

64

Burst Length

4*

8

4

CAS Latency

1

2

3

1

2

3

1

2

3

Area 2

H'FF900048

H'FF900088

H'FF9000C8

H'FF90004C

H'FF90008C

H'FF9000CC

H'FF900090

H'FF900110

H'FF900190

Area 3

H'FF940048

H'FF940088

H'FF9400C8

H'FF94004C

H'FF94008C

H'FF9400CC

H'FF940090

H'FF940110

H'FF940190

For a 32-bit bus:

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address 0 0 0 0 0 0 0 0 0 LMO LMO LMO WT BL2 BL1 BL0

DE2 DE1 DE0

âï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§â

10 bits set in case of 32-bit bus width

For a 64-bit bus:

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address 0 0 0 0 0 0 0 0 LMO LMO LMO WT BL2 BL1 BL0

DE2 DE1 DE0

âï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§ï£§â

10 bits set in case of 64-bit bus width

Rev. 6.0, 07/02, page 363 of 986

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