HD6417750 Datasheet, PDF (365/1039 Pages) Renesas Technology Corp – SuperH RISC engine

13.1.2 Block Diagram
Figure 13.1 shows a block diagram of the BSC.
Bus
interface
–
–
RD/
–
,
CKE
,
Interrupt
controller
Wait
control unit
Area
control unit
Memory
control unit
Refresh
control unit
WCR1
WCR2
WCR3
BCR1
BCR2
BCR3*
BCR4*
MCR
PCR
RFCR
RTCNT
Comparator
RTCOR
RTCSR
WCR: Wait control register
BCR: Bus control register
MCR: Memory control register
PCR: PCMCIA control register
RFCR: Refresh count register
RTCNT: Refresh timer count register
RTCOR: Refresh time constant register
RTCSR: Refresh timer control/status register
Note: * SH7750R only
Figure 13.1 Block Diagram of BSC
BSC
Rev. 6.0, 07/02, page 313 of 986