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HD6417750 Datasheet, PDF (900/1039 Pages) Renesas Technology Corp – SuperH RISC engine | |||
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Table 22.27 Clock and Control Signal Timing (HD6417750RBP200)
VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = â20 to +75°C, CL = 30 pF
Item
Symbol Min
EXTAL
PLL1 6-times/PLL2
fEX
16
clock input operation
frequency PLL1 12-times/PLL2
f
14
EX
operation
PLL1/PLL2 not operating f
1
EX
EXTAL clock input cycle time
t
30
EXcyc
EXTAL clock input low-level pulse width t
3.5
EXL
EXTAL clock input high-level pulse width t
3.5
EXH
EXTAL clock input rise time
tEXr
â
EXTAL clock input fall time
tEXf
â
CKIO clock PLL1/PLL2 operating
fOP
25
output
PLL1/PLL2 not operating f
1
OP
CKIO clock output cycle time
t
10
cyc
CKIO clock output low-level pulse width tCKOL1
1
CKIO clock output high-level pulse width tCKOH1
1
CKIO clock output rise time
tCKOr
â
CKIO clock output fall time
t
â
CKOf
CKIO clock output low-level pulse width t
3
CKOL2
CKIO clock output high-level pulse width t
3
CKOH2
Power-on oscillation settling time
t
10
OSC1
Power-on oscillation settling time/mode tOSCMD
10
settling
SCK2 reset setup time
SCK2 reset hold time
MD reset setup time
MD reset hold time
5(6(7 assert time
t
20
SCK2RS
tSCK2RH
20
tMDRS
3
tMDRH
20
tRESW
20
PLL synchronization settling time
t
200
PLL
Standby return oscillation settling time 1 tOSC2
5
Standby return oscillation settling time 2 tOSC3
5
Standby return oscillation settling time 3 t
5
OSC4
Max Unit Figure
34
MHz
17
34
1000
â
â
4
4
100
100
1000
â
â
3
3
â
â
â
â
ns
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ms
ms
22.1
22.1
22.1
22.1
22.1
22.2(1)
22.2(1)
22.2(1)
22.2(1)
22.2(1)
22.2(2)
22.2(2)
22.3, 22.5
22.3, 22.5
â
ns 22.11
â
ns 22.3, 22.5, 22.11
â
tcyc
22.12
â
ns 22.3, 22.5, 22.12
â
tcyc
22.3, 22.4, 22.5,
22.6, 22.11
â
µs 22.9, 22.10
â
ms 22.4, 22.6
â
ms 22.7
â
ms 22.8
Rev. 6.0, 07/02, page 848 of 986
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