 English |
|
|
|
|
|
|
|
| HD6417750 Datasheet, PDF (953/1039 Pages) Renesas Technology Corp – SuperH RISC engine | |||
| |||
| ◁ |
CKIO
A25âA0
RD/
T1r
Tr2
Tc1
Tc2
Tce
Tpc
tAD
Row
tCSD
tAD
Column
tAD
tCSD
tRWD
tRASD tRASD
tRWD
tRASD
tCASD1
tCASD1
tCASD1
D63âD0
(read)
D63âD0
(write)
tWDD
tRDS
tRDH
tBSD
tBSD
DACKn
(SA: IO â memory)
tDACD tDACD
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 22.38 DRAM Bus Cycle
(EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001)
Rev. 6.0, 07/02, page 901 of 986
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese