HD6417750 Datasheet, PDF (503/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Card 1
on CS5
Virtual
address space
Common
memory 1
Common
memory 2
Attribute memory
I/O space 1
I/O space 2
Card 2
on CS6
Common memory
(64 MB)
Access
by CS5 wait
controller
Access
by CS6 wait
controller
Virtual
address space
1 kB IO 1
page
Physical I/O
addresses
IO 1
IO 2
Attribute memory
(64 MB)
.
.
.
I/O space
(64 MB)
IO 2
1 kB
page
Different virtual pages
mapped to the same
physical page
Example of I/O spaces with different cycle times
(less than 1 kB)
.
.
.
The page size can be 1 kB, 4 kB, 64 kB, or 1 MB.
Example of PCMCIA interface mapping
Figure 13.52 PCMCIA Space Allocation
I/O Card Interface Timing: Figures 13.53 and 13.54 show the timing for the PCMCIA I/O card
interface.
When an I/O card interface access is made to a PCMCIA card in little-endian mode, dynamic
sizing of the I/O bus width is possible using the ,2,649 pin. When a 16-bit bus width is set, if the
,2,649 signal is high during a word-size I/O bus cycle, the I/O port is recognized as being 8 bits
in width. In this case, a data access for only 8 bits is performed in the I/O bus cycle being
executed, followed automatically by a data access for the remaining 8 bits. Dynamic bus sizing is
also performed in the case of byte-size access to address 2n + 1.
Figure 13.55 shows the basic timing for dynamic bus sizing.
Rev. 6.0, 07/02, page 451 of 986