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HD6417750 Datasheet, PDF (393/1039 Pages) Renesas Technology Corp – SuperH RISC engine | |||
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Bits 31, 27, 23, 19, 15, 11, 7, and 3âReserved: These bits are always read as 0, and should only
be written with 0.
Bits 30 to 28â DMAIW-DACK Device Inter-Cycle Idle Specification (DMAIW2â
DMAIW0): These bits specify the number of idle cycles between bus cycles to be inserted when
switching from a DACK device to another space, or from a read access to a write access on the
same device. The DMAIW bits are valid only for DMA single address transfer; with DMA dual
address transfer, inter-area idle cycles are inserted.
Bits 4n + 2 to 4nâArea n (6 to 0) Inter-Cycle Idle Specification (AnlW2âAnlW0): These bits
specify the number of idle cycles between bus cycles to be inserted when switching from external
memory space area n (n = 6 to 0) to another space, or from a read access to a write access in the
same space.
DMAIW2/AnIW2
0
1
DMAIW1/AnIW1
0
1
0
1
DMAIW0/AnIW0
0
1
0
1
0
1
0
1
Inserted Idle Cycles
0
1
2
3
6
9
12
15
(Initial value)
Rev. 6.0, 07/02, page 341 of 986
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