HD6417750 Datasheet, PDF (628/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Table 14.12 DMAC Pins in DDT Mode
Pin Name
Data bus request
Data bus available
Abbreviation
'%5(4
('5(43)
%$9//,'5
(DRAK0)
Transfer request signal 75
('5(44)
DMAC strobe
Channel number
notification
7'$&.
(DACK0)
ID[1:0]
(DRAK1, DACK1)
I/O
Input
Output
Input
Output
Output
Function
Data bus release request from external
device for DTR format input
Data bus release notification
Data bus can be used 2 cycles after
%$9/ is asserted
Notification of channel number to
external device at same time as 7'$&.
output
If asserted 2 cycles after %$9/
assertion, DTR format is sent
Only 75 asserted: DMA request
'%5(4 and 75 asserted
simultaneously: Direct request to
channel 2
Reply strobe signal for external device
from DMAC
Notification of channel number to
external device at same time as 7'$&.
output
(ID [1] = DRAK1, ID [0] = DACK1)
Requests for DMA transfer from external devices are normally accepted only on channel 0
('5(43) and channel 1 ('5(44). In DDT mode, the %$9/ pin functions as both the data-bus-
available pin and channel-number-notification (,'5) pin.
14.6.3 Register Configuration (SH7750R)
Table 14.13 shows the configuration of the DMAC’s registers. The DMAC of the SH7750R has a
total of 33 registers: four registers are assigned to each channel, and there is a control register for
the overall control of the DMAC.
Rev. 6.0, 07/02, page 576 of 986