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HD6417750 Datasheet, PDF (977/1039 Pages) Renesas Technology Corp – SuperH RISC engine
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Module Item
I/O
ports
Output data
delay time
Input data
setup time
Input data
hold time
DMAC '5(4Q
setup time
'5(4Q
hold time
DRAKn
delay time
INTC
NMI pulse
width (high)
NMI pulse
width (low)
Symbol
t
PORTD
HD6417750
RBP240
*2
Min Max
1.5 5.3
t
PORTS
2
—
t
PORTH
1.5 —
t
DRQS
2
—
t
DRQH
1.5 —
t
DRAKD
1.5 5.3
t
NMIH
5
—
30 —
t
NMIL
5
—
30 —
HD6417750
RBP200
*2
Min Max
1.5 6
2.5 —
1.5 —
2.5 —
1.5 —
1.5 6
5
—
30 —
5
—
30 —
HD6417750
RF240
*2
Min Max
1.5 6
3.5 —
1.5 —
3.5 —
1.5 —
1.5 6
5
—
30 —
5
—
30 —
HD6417750
RF200
*2
Min Max Unit
1.5 6
ns
3.5 — ns
1.5 — ns
3.5 — ns
1.5 — ns
1.5 6
ns
5
—t
cyc
30 — ns
5
—t
cyc
30 — ns
Figure
22.65
22.65
22.65
22.66
22.66
22.66
22.71
22.71
Normal
or sleep
mode
Standby
mode
22.71
22.71
Normal
or sleep
mode
Standby
mode
H-UDI
Input clock
cycle
t
TCKcyc
50 —
50 —
50 —
50 —
Input clock
t
TCKH
pulse width
(high)
15 —
15 —
15 —
15 —
Input clock t
TCKL
pulse width
(low)
15 —
15 —
15 —
15 —
Input clock t
TCKr
rise time
— 10
— 10
— 10
— 10
Input clock t
TCKf
fall time
— 10
— 10
— 10
— 10
$6(%5.
setup time
t
ASEBRKS
10 —
10 —
10 —
10 —
$6(%5.
hold time
t
ASEBRKH
10 —
10 —
10 —
10 —
TDI/TMS
t
TDIS
setup time
15 —
15 —
15 —
15 —
TDI/TMS
t
TDIH
hold time
15 —
15 —
15 —
15 —
TDO delay
t
TDO
time
0
10
0
10
0
10
0
10
ASE-PINBRK t
PINBRK
2
—
pulse width
2
—
2
—
2
—
Notes: *1 Pcyc: P clock cycles
*2 VDDQ = 3.0 to 3.6 V, VDD = 1.5 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on
ns
22.67
ns
22.67
ns
22.67
ns
22.67
ns
22.67
t
22.68
cyc
t
22.68
cyc
ns
22.69
ns
22.69
ns
22.69
Pcyc*1 22.70
Rev. 6.0, 07/02, page 925 of 986
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