HD6417750 Datasheet, PDF (42/1039 Pages) Renesas Technology Corp – SuperH RISC engine

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Dual Address Mode/Synchronous DRAM → SRAM Longword Transfer...... 553
Single Address Mode/Burst Mode/External Bus → External Device 32-Byte
Block Transfer/Channel 0 On-Demand Data Transfer..................................... 554
Single Address Mode/Burst Mode/External Device → External Bus 32-Byte
Block Transfer/Channel 0 On-Demand Data Transfer..................................... 554
Single Address Mode/Burst Mode/External Bus → External Device 32-Bit
Transfer/Channel 0 On-Demand Data Transfer ............................................... 555
Single Address Mode/Burst Mode/External Device → External Bus 32-Bit
Transfer/Channel 0 On-Demand Data Transfer ............................................... 556
Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer) 557
Handshake Protocol without Use of Data Bus (Channel 0 On-Demand Data
Transfer)........................................................................................................... 558
Read from Synchronous DRAM Precharge Bank ............................................ 559
Read from Synchronous DRAM Non-Precharge Bank (Row Miss) ................ 559
Read from Synchronous DRAM (Row Hit) ..................................................... 560
Write to Synchronous DRAM Precharge Bank................................................ 560
Write to Synchronous DRAM Non-Precharge Bank (Row Miss).................... 561
Write to Synchronous DRAM (Row Hit)......................................................... 561
Single Address Mode/Burst Mode/External Bus → External Device 32-Byte
Block Transfer/Channel 0 On-Demand Data Transfer..................................... 562
DDT Mode Setting ........................................................................................... 563
Single Address Mode/Burst Mode/Edge Detection/ External Device →
External Bus Data Transfer .............................................................................. 563
Single Address Mode/Burst Mode/Level Detection/ External Bus →
External Device Data Transfer ......................................................................... 564
Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword,
Quadword/External Bus → External Device Data Transfer............................. 564
Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword,
Quadword/External Device → External Bus Data Transfer............................. 565
Single Address Mode/Burst Mode/32-Byte Block Transfer/DMA Transfer
Request to Channels 1–3 Using Data Bus ........................................................ 566
Single Address Mode/Burst Mode/32-Byte Block Transfer/ External Bus →
External Device Data Transfer/ Direct Data Transfer Request to Channel 2
without Using Data Bus ................................................................................... 567
Single Address Mode/Burst Mode/External Bus → External Device Data
Transfer/Direct Data Transfer Request to Channel 2 ....................................... 568
Single Address Mode/Burst Mode/External Device → External Bus Data
Transfer/Direct Data Transfer Request to Channel 2 ....................................... 569
Single Address Mode/Burst Mode/External Bus → External Device Data
Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2.. 570
Single Address Mode/Burst Mode/External Device → External Bus Data
Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2.. 571
Block Diagram of the DMAC .......................................................................... 574
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