HD6417750 Datasheet, PDF (160/1039 Pages) Renesas Technology Corp – SuperH RISC engine

4.3.9 Prefetch Operation
The SH7750 Series supports a prefetch instruction to reduce the cache fill penalty incurred as the
result of a cache miss. If it is known that a cache miss will result from a read or write operation, it
is possible to fill the cache with data beforehand by means of the prefetch instruction to prevent a
cache miss due to the read or write operation, and so improve software performance. If a prefetch
instruction is executed for data already held in the cache, or if the prefetch address results in a
UTLB miss or a protection violation, the result is no operation, and an exception is not generated.
Details of the prefetch instruction are given in the Programming Manual.
Prefetch instruction:
PREF @Rn
4.4 Instruction Cache (IC)
4.4.1 Configuration
The instruction cache of the SH7750 or SH7750S is of the direct-mapping type and consists of
256 cache lines, each composed of a 19-bit tag, V bit, and 32-byte data (16 instructions). The
SH7750R’s instruction cache is 2-way set associative. Each way consists of 256 cache lines.
Figure 4.6 shows the configuration of the instruction cache for the SH7750 and SH7750S.
Figure 4.7 shows the configuration of the instruction cache for the SH7750R.
Rev. 6.0, 07/02, page 108 of 986