HD6417750 Datasheet, PDF (653/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor
format is selected, the PE bit and O/( bit parity settings are invalid. The MP bit setting is only
valid in asynchronous mode; it is invalid in synchronous mode.
For details of the multiprocessor communication function including notes on use, see section
15.3.3, Multiprocessor Communication Function.
Bit 2: MP
0
1
Description
Multiprocessor function disabled
Multiprocessor format selected
(Initial value)
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the on-
chip baud rate generator. The clock source can be selected from Pφ, Pφ/4, Pφ/16, and Pφ/64,
according to the setting of bits CKS1 and CKS0.
For the relation between the clock source, the bit rate register setting, and the baud rate, see
section 15.2.9, Bit Rate Register (SCBRR1).
Bit 1: CKS1 Bit 0: CKS0
0
0
1
1
0
1
Note: Pφ: Peripheral clock
Description
Pφ clock
Pφ/4 clock
Pφ/16 clock
Pφ/64 clock
(Initial value)
15.2.6 Serial Control Register (SCSCR1)
Bit: 7
6
5
TIE
RIE
TE
Initial value: 0
0
0
R/W: R/W R/W R/W
4
3
2
1
0
RE MPIE TEIE CKE1 CKE0
0
0
0
0
0
R/W R/W R/W R/W R/W
The SCSCR1 register performs enabling or disabling of SCI transfer operations, serial clock
output in asynchronous mode, and interrupt requests, and selection of the serial clock source.
SCSCR1 can be read or written to by the CPU at all times.
SCSCR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the
module standby state.
Rev. 6.0, 07/02, page 601 of 986