HD6417750 Datasheet, PDF (912/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Table 22.33 Clock and Control Signal Timing (HD6417750VF128)
V_DDQ = 3.0 to 3.6 V, V_DD = 1.5 V, T_a = –20 to +75°C, C_L = 30 pF
Item
Symbol Min
EXTAL
PLL2
1/2 divider
f_EX
16
clock input operating operating
frequency
1/2 divider not f
8
EX
operating
PLL2
1/2 divider
f
2
EX
not
operating
operating _{1/2 divider not f}
1
EX
operating
EXTAL clock input cycle time
t_EXcyc
23
EXTAL clock input low-level pulse width t
3.5
EXL
EXTAL clock input high-level pulse width t
3.5
EXH
EXTAL clock input rise time
t_EXr
—
EXTAL clock input fall time
t_EXf
—
CKIO clock PLL2 operating
f
25
OP
output
PLL2 not operating
f
1
OP
CKIO clock output cycle time
t
15
cyc
CKIO clock output low-level pulse width t
1
CKOL1
CKIO clock output high-level pulse width t_CKOH1
1
CKIO clock output rise time
t_CKOr
—
CKIO clock output fall time
t_CKOf
—
CKIO clock output low-level pulse width t
3
CKOL2
CKIO clock output high-level pulse width t
3
CKOH2
Power-on oscillation settling time
t_OSC1
10
Power-on oscillation settling time/mode t_OSCMD
10
settling
SCK2 reset setup time
SCK2 reset hold time
MD reset setup time
MD reset hold time
5(6(7 assert time
t
20
SCK2RS
t
20
SCK2RH
t_MDRS
3
t_MDRH
20
t_RESW
20
PLL synchronization settling time
t_PLL
200
Max Unit Figure
43
MHz
22
43
22
1000
—
—
4
4
64
64
1000
—
—
3
3
—
—
—
—
ns
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ms
ms
22.1
22.1
22.1
22.1
22.1
22.2(1)
22.2(1)
22.2(1)
22.2(1)
22.2(1)
22.2(2)
22.2(2)
22.3, 22.5
22.3, 22.5
—
ns 22.11
—
ns 22.3, 22.5, 22.11
—
t_cyc
22.12
—
ns 22.3, 22.5, 22.12
—
t_cyc
22.3, 22.4, 22.5,
22.6, 22.11
—
µs 22.9, 22.10
Rev. 6.0, 07/02, page 860 of 986