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HD6417750 Datasheet, PDF (372/1039 Pages) Renesas Technology Corp – SuperH RISC engine | |||
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Table 13.3 External Memory Space Map
Area
External
Addresses
Size
Connectable
Memory
Settable Bus
Widths
Access Size
0
H'00000000â 64 Mbytes SRAM
H'03FFFFFF
Burst ROM
MPX
8, 16, 32, 64*1
8, 16, 32*1, 64*7
32, 64*1
8,16,32,
64*6 bits,
32 bytes
1
H'04000000â 64 Mbytes SRAM
8, 16, 32, 64*2 8,16,32,
H'07FFFFFF
MPX
32, 64*2
Byte control SRAM 16, 32, 64*2
64*6 bits,
32 bytes
2
H'08000000â 64 Mbytes SRAM
8, 16, 32, 64*2 8,16,32,
H'0BFFFFFF
Synchronous DRAM 32, 64*2 *3
DRAM
16, 32*2 *3
64*6 bits,
32 bytes
MPX
32, 64*2
3
H'0C000000â 64 Mbytes SRAM
8, 16, 32, 64*2 8,16,32,
H'0FFFFFFF
Synchronous DRAM 32, 64*2 *3
DRAM
16, 32, 64*2 *3
64*6 bits,
32 bytes
MPX
32, 64*2
4
H'10000000â 64 Mbytes SRAM
8, 16, 32, 64*2 8,16,32,
H'13FFFFFF
MPX
Byte control RAM
32, 64*2
16, 32, 64*2
64*6 bits,
32 bytes
5
H'14000000â 64 Mbytes SRAM
H'17FFFFFF
MPX
Burst ROM
8, 16, 32, 64*2
32, 64*2
8, 16, 32*2, 64*7
8,16,32,
64*6 bits,
32 bytes
PCMCIA
8, 16*2 *4
6
H'18000000â 64 Mbytes SRAM
H'1BFFFFFF
MPX
Burst ROM
8, 16, 32, 64*2
32, 64*2
8,16, 32*2, 64*7
8,16,32,
64*6 bits,
32 bytes
PCMCIA
8,16*2 *4
7*5
H'1C000000â 64 Mbytes â
â
H'1FFFFFFF
Notes: *1 Memory bus width specified by external pins
*2 Memory bus width specified by register
*3 With synchronous DRAM interface, bus width is 32 or 64 bits only.
With DRAM interface, bus width is 16 or 32 bits only for area 2, and 16, 32, or 64 bits
only for area 3. Bus width of area 2 is as same as that of area 3 which is specified by
MCR.
*4 With PCMCIA interface, bus width is 8 or 16 bits only.
*5 Do not access a reserved area, as operation cannot be guaranteed in this case.
*6 64-bit access applies only to transfer by the DMAC. (CHCRn. TS = 000)
In a transfer to an external memory by FMOV (FPSCR.SZ = 1), two transfer operations,
each with an access size of 32 bits, are conducted.
*7 Settable only for SH7750R.
Rev. 6.0, 07/02, page 320 of 986
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