HD6417750 Datasheet, PDF (636/1039 Pages) Renesas Technology Corp – SuperH RISC engine

DMAOR is initialized to H'00000000 by a power-on or manual reset. They retain their values in
standby mode and deep sleep mode.
Bits 31 to 16—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 15—On-Demand Data Transfer (DDT): Specifies on-demand data transfer mode. For
details of the settings, see the description of the DDT bit in section 14.2.5, DMA Operation
Register (DMAOR)
Bit 14Number of DDT-Mode Channels (DBL): Selects the number of channels that are able
to accept external requests in DDT mode.
Bit 14: DBL
Description
0
Four DDT-mode channels
1
Eight DDT-mode channels
Note: When DMAOR.DBL = 0, channels 4 to 7 cannot accept external requests.
(Initial value)
When DMAOR.DBL = 1, one channel can be selected from among channels 0–7 by the
combination of DTR.SZ and DTR.ID in the DTR format (see figure 14.54). Table 14.14 shows the
channel selection by DTR format in the DDT mode.
Table 14.14 Channel Selection by DTR Format (DMAOR.DBL = 1)
DTR.ID[1:0]
00
01
10
11
DTR.SZ[2:0] ≠ 101
CH0
CH1
CH2
CH3
DTR.SZ[2:0] = 101
CH4
CH5
CH6
CH7
63 61 60 59 58 57 56 55
48 47
32 31
0
SZ R/W ID MD COUNT (Reserved)
ADDRESS
Figure 14.54 DTR Format (Transfer Request Format) (SH7750R)
Bits 13 to 10—Reserved: These bits are always read as 0, and should only be written with 0.
Bits 9 and 8—Priority Mode 1 and 0 (PR1, PR0): These bits determine the order of priority for
channel execution when transfer requests are made for a number of channels simultaneously.
Rev. 6.0, 07/02, page 584 of 986