HD6417750 Datasheet, PDF (976/1039 Pages) Renesas Technology Corp – SuperH RISC engine

22.3.4 Peripheral Module Signal Timing
Table 22.36 Peripheral Module Signal Timing (1)
Module
TMU,
RTC
SCI
Item
Symbol
Timer clock
pulse width
(high)
t
TCLKWH
Timer clock
pulse width
(low)
t
TCLKWL
Timer clock
t
TCLKr
rise time
Timer clock
t
TCLKf
fall time
Oscillation t
ROSC
settling time
Input clock t
Scyc
cycle (asyn-
chronous)
Input clock
t
Scyc
cycle (syn-
chronous)
Input clock
t
SCKW
pulse width
Input clock t
SCKr
rise time
Input clock t
SCKf
fall time
Transfer data t
TXD
delay time
Receive data t
RXS
setup time
(synchronous)
Receive data t
RXH
hold time
(synchronous)
HD6417750
RBP240
*²
Min Max
4
—
4
—
— 0.8
— 0.8
—3
4
—
6
—
0.4 0.6
— 0.8
— 0.8
1.5 5.3
16 —
16 —
HD6417750
RBP200
*²
Min Max
4
—
4
—
— 0.8
— 0.8
—3
4
—
6
—
0.4 0.6
— 0.8
— 0.8
1.5 6
16 —
16 —
HD6417750
RF240
*²
Min Max
4
—
4
—
— 0.8
— 0.8
—3
4
—
6
—
0.4 0.6
— 0.8
— 0.8
1.5 6
16 —
16 —
HD6417750
RF200
*²
Min Max Unit Figure
4
— Pcyc*¹ 22.61
4
— Pcyc*¹ 22.61
— 0.8 Pcyc*¹ 22.61
— 0.8 Pcyc*¹ 22.61
—3
s
22.62
4
— Pcyc*¹ 22.63
6
— Pcyc*¹ 22.63
0.4 0.6 t
Scyc
22.63
— 0.8 Pcyc*¹ 22.63
— 0.8 Pcyc*¹ 22.63
1.5 6
ns
22.64
16 — ns
22.64
16 — ns
22.64
Rev. 6.0, 07/02, page 924 of 986