HD6417750 Datasheet, PDF (979/1039 Pages) Renesas Technology Corp – SuperH RISC engine

HD6417750
SVF133
HD6417750
SVBT133
*²
HD6417750
SF167
HD6417750
SF167I
HD6417750
SF200
*³
HD6417750
SBP200
*⁴
Module Item
Symbol Min Max Min Max Min Max Unit Figure
DMAC '5(4Q
t
DRQS
setup time
3.5 —
3.5 —
3
— ns
22.66
'5(4Q
t
1.5 —
1.5 —
1.5 — ns
22.66
DRQH
hold time
INTC
DRAKn
delay time
NMI pulse
width (high)
NMI pulse
width (low)
t
DRAKD
t
NMIH
t
NMIL
1.5 10
5
—
30 —
5
—
30 —
1.5 8
5
—
30 —
5
—
30 —
1.5 6
ns
5
—t
cyc
30 — ns
5
—t
cyc
30 — ns
22.66
22.71
22.71
22.71
22.71
Normal or sleep mode
Standby mode
Normal or sleep mode
Standby mode
H-UDI
Input clock
cycle
t
TCKcyc
50 —
50 —
50 — ns
22.67
Input clock t
TCKH
pulse width
(high)
15 —
15 —
15 — ns
22.67
Input clock t
TCKL
pulse width
(low)
15 —
15 —
15 — ns
22.67
Input clock t
TCKr
rise time
— 10
— 10
— 10 ns
22.67
Input clock
t
TCKf
fall time
— 10
— 10
— 10 ns
22.67
$6(%5.
setup time
t
ASEBRKS
10 —
10 —
10 — t
cyc
22.68
$6(%5.
hold time
t
ASEBRKH
10 —
10 —
10 — t
cyc
22.68
TDI/TMS
t
TDIS
setup time
15 —
15 —
15 — ns
22.69
TDI/TMS
t
TDIH
hold time
15 —
15 —
15 — ns
22.69
TDO delay t
TDO
time
0
10
0
10
0
10 ns
22.69
ASE-PINBRK t
PINBRK
2
—
pulse width
2
—
2
— Pcyc*¹ 22.70
Notes: *1 Pcyc: P clock cycles
*2 V_DDQ = 3.0 to 3.6 V, V_DD = typ. 1.5 V, Ta = –20 to +75°C, C_L = 30 pF, PLL2 on
*3 V_DDQ = 3.0 to 3.6 V, V_DD = typ. 1.8 V, Ta = –20 to +75°C, C_L = 30 pF, PLL2 on
(HD6417750SF167, HD6417750SF200)
V_DDQ = 3.0 to 3.6 V, V_DD = typ. 1.8 V, Ta = –40 to +85°C, C_L = 30 pF, PLL2 on
(HD6417750SF167I)
*4 V_DDQ = 3.0 to 3.6 V, V_DD = typ. 1.8 V, Ta = –20 to +75°C, C_L = 30 pF, PLL2 on
Rev. 6.0, 07/02, page 927 of 986