HD6417750 Datasheet, PDF (440/1039 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
A25–A0
RD/
D63–D0
(read)
D63–D0
(write)
T1
T2
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
DACKn
(DA)
SA: Single address DMA
DA: Dual address DMA
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.6 Basic Timing of SRAM Interface
Rev. 6.0, 07/02, page 388 of 986