HD6417750 Datasheet, PDF (534/1039 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
A25–A0
RD/
D63–D0 (write)
/
/
A25–A0
RD/
D63–D0 (write)
Asserted for at least 2 cycles
Negated within 2 cycles
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
Master mode device access
Must be asserted for
at least 2 cycles
Must be negated within 2 cycles
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
Slave mode device access
Master access
Slave access
Figure 13.78 Arbitration Sequence
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
Master access
Rev. 6.0, 07/02, page 482 of 986