HD6417750 Datasheet, PDF (460/1039 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
A25–A0
RD/
D63–D0
(read)
Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tce
c1
c2
c3
c4
End of RAS down mode
d1
d2
d3
d4
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.22 (4) DRAM Burst Bus Cycle, RAS Down Mode Continuation
(EDO Mode, RCD = 0, AnW = 0)
Rev. 6.0, 07/02, page 408 of 986