HD6417750 Datasheet, PDF (378/1039 Pages) Renesas Technology Corp – SuperH RISC engine

13.2 Register Descriptions
13.2.1 Bus Control Register 1 (BCR1)
Bus control register 1 (BCR1) is a 32-bit readable/writable register that specifies the function, bus
cycle status, etc., of each area.
BCR1 is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or
in standby mode. External memory space other than area 0 should not be accessed until register
initialization is completed.
Bit: 31
30
29
28
ENDIAN MASTER A0MPX
—
Initial value: ^0/1*1
0/1*¹
0/1*¹
0
R/W: R
R
R
R
27
26
25
24
— DPUP*² IPUP OPUP
0
0
0
0
R
R
R/W
R/W
Bit: 23
—
Initial value:
0
R/W: R
22
21
20
19
18
17
16
—
A1MBC A4MBC BREQEN PSHR MEMMPX DMABST*²
0
0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R
Bit: 15
HIZMEM
Initial value:
0
R/W: R/W
14
HIZCNT
0
R/W
13
A0BST2
0
R/W
12
A0BST1
0
R/W
11
A0BST0
0
R/W
10
A5BST2
0
R/W
9
A5BST1
0
R/W
8
A5BST0
0
R/W
Bit:
7
6
5
4
3
2
1
0
A6BST2 A6BST1 A6BST0 DRAMTP2 DRAMTP1 DRAMTP0 —
A56PCM
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Notes: *1 These bits sample external pin values in a power-on reset by means of the 5(6(7 pin.
*2 SH7750R only.
Rev. 6.0, 07/02, page 326 of 986