HD6417750 Datasheet, PDF (373/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Area 0: H'00000000 SRAM/burst ROM/MPX
Area 1: H'04000000 SRAM/MPX/byte control SRAM
Area 2: H'08000000
Area 3: H'0C000000
Area 4: H'10000000
SRAM/synchronous DRAM/DRAM/
MPX
SRAM/synchronous DRAM/DRAM/
MPX
SRAM/MPX/byte control SRAM
Area 5: H'14000000 SRAM/burst ROM/PCMCIA/MPX
Area 6: H'18000000 SRAM/burst ROM/PCMCIA/MPX
The PCMCIA interface is
for memory and I/O card use
Figure 13.3 External Memory Space Allocation
Memory Bus Width: In the SH7750 Series, the memory bus width can be set independently for
each space. For area 0, a bus size of 8, 16, 32, or 64 bits can be selected in a power-on reset by the
5(6(7 pin, using external pins. The relationship between the external pins (MD4 and MD3) and
the bus width in a power-on reset is shown below.
MD4
0
1
MD3
0
1
0
1
Bus Width
64 bits
8 bits
16 bits
32 bits
When SRAM interface or ROM is used in areas 1 to 6, a bus width of 8, 16, 32, or 64 bits can be
selected with bus control register 2 (BCR2). When burst ROM is used, a bus width of 8, 16, 32, or
64* bits can be selected. When byte control SRAM interface is used, a bus width of 16, 32, or 64
bits can be selected. When the MPX interface is used, a bus width of 32 or 64 bits can be selected.
When the DRAM interface is used, a bus width of 16, 32, or 64 bits can be selected with the
memory control register (MCR). When the DRAM interface is used for area 2 or 3, a bus width of
16 or 32 bits should be set. For the synchronous DRAM interface, set a bus width of 32 or 64 bits
in the MCR register.
Rev. 6.0, 07/02, page 321 of 986