HD6417750 Datasheet, PDF(221/1039 Page) Renesas Technology Corp – SuperH RISC engine

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

HD6417750 Datasheet, PDF (221/1039 Pages) Renesas Technology Corp – SuperH RISC engine

◁

Round to Zero: The digits below the round bit of the unrounded value are discarded.

If the unrounded value is larger than the maximum expressible absolute value, the value will be

the maximum expressible absolute value.

6.5 Floating-Point Exceptions

FPU-related exceptions are as follows:

â¢ General illegal instruction/slot illegal instruction exception

The exception occurs if an FPU instruction is executed when SR.FD = 1.

â¢ FPU exceptions

The exception sources are as follows:

ï£§ FPU error (E): When FPSCR.DN = 0 and a denormalized number is input

ï£§ Invalid operation (V): In case of an invalid operation, such as NaN input

ï£§ Division by zero (Z): Division with a zero divisor

ï£§ Overflow (O): When the operation result overflows

ï£§ Underflow (U): When the operation result underflows

ï£§ Inexact exception (I): When overflow, underflow, or rounding occurs

The FPSCR cause field contains bits corresponding to all of above sources E, V, Z, O, U, and

I, and the FPSCR flag and enable fields contain bits corresponding to sources V, Z, O, U, and

I, but not E. Thus, FPU errors cannot be disabled.

When an exception source occurs, the corresponding bit in the cause field is set to 1, and 1 is

added to the corresponding bit in the flag field. When an exception source does not occur, the

corresponding bit in the cause field is cleared to 0, but the corresponding bit in the flag field

remains unchanged.

â¢ Enable/disable exception handling

The SH7750 Series supports enable exception handling and disable exception handling.

Enable exception handling is initiated in the following cases:

ï£§ FPU error (E): FPSCR.DN = 0 and a denormalized number is input

ï£§ Invalid operation (V): FPSCR.EN.V = 1 and (instruction = FTRV or invalid operation)

ï£§ Division by zero (Z): FPSCR.EN.Z = 1 and division with a zero divisor

ï£§ Overflow (O): FPSCR.EN.O = 1 and instruction with possibility of operation result

overflow

ï£§ Underflow (U): FPSCR.EN.U = 1 and instruction with possibility of operation result

underflow

ï£§ Inexact exception (I): FPSCR.EN.I = 1 and instruction with possibility of inexact operation

result

Rev. 6.0, 07/02, page 169 of 986

▷