HD6417750 Datasheet, PDF (448/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Signals used for connection when DRAM is connected to area 3 are 5$6, &$63 to &$6:, and
RD/:5. &$65 to &$6: are not used when the data width is 16 bits. When DRAM is connected
to areas 2 and 3, the signals for area 2 DRAM connection are 5$65, &$67 to &$6:, and RD/:5,
and those for area 3 DRAM connection are 5$6, &$63 to &$66, and RD/:5.
In addition to normal read and write access modes, fast page mode is supported for burst access.
For DRAM connected to areas 2 and 3, EDO mode, which enables the DRAM access time to be
increased, is supported.
SH7750 Series
A12–A3
RD/
D63–D48
1M × 16-bit
DRAM
A9–A0
I/O15–I/O0
D47–D32
A9–A0
I/O15–I/O0
D31–D16
A9–A0
I/O15–I/O0
D15–D0
A9–A0
I/O15–I/O0
Figure 13.14 Example of DRAM Connection (64-Bit Data Width, Area 3)
Rev. 6.0, 07/02, page 396 of 986