HD6417750 Datasheet, PDF (20/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Section
22.3.1 Clock and Control
Signal Timing
Page
850, 851
852, 853
854, 855
856, 857
858, 859
860, 861
864
865
866
22.3.2 Control Signal Timing 868
22.3.3 Bus Timing
880
881
871, 872
Item
Description
Table 22.28 Clock and
Control Signal Timing
(HD6417750RF200)
Newly added
Table 22.29 Clock and
Control Signal Timing
(HD6417750BP200M,
HD6417750SBP200)
Newly added
Table 22.30 Clock and
Control Signal Timing
(HD6417750SF200)
Amended
Table 22.31 Clock and
Control Signal Timing
(HD6417750F167,
HD6417750F167I,
HD6417750SF167,
HD6417750SF167I)
Amended
Table 22.32 Clock and
Control Signal Timing
(HD6417750SVF133,
HD6417750SVBT133)
Amended
Table 22.33 Clock and
Control Signal Timing
(HD6417750VF128)
Amended
Figure 22.6 Standby Return
Oscillation Settling Time
(Return by 5(6(7)
Amended
Figure 22.8 Standby Return
Oscillation Settling Time
(Return by ,5/6–,5/3)
Amended
Figure 22.10 PLL
Amended
Synchronization Settling Time
in Case of IRL Interrupt
Table 22.34 Control Signal Table newly added
Timing (1)
Figure 22.18 SRAM Bus
Cycle: Basic Bus Cycle (No
Wait, Address Setup/Hold
Time Insertion, AnS = 1,
AnH = 1)
Figure changed and
Note added
Figure 22.19 Burst ROM
Bus Cycle (No Wait)
Amended
Table 22.35 Bus Timing (1) Table newly added
Rev. 6.0, 07/02, page xviii of I