HD6417750 Datasheet, PDF (577/1039 Pages) Renesas Technology Corp – SuperH RISC engine

(a) Normal DMA Mode
Table 14.8 shows the memory interfaces that can be specified for the transfer source and transfer
destination in DMA transfer initiated by an external request supported by the SH7750 Series in
normal DMA mode.
Table 14.8 External Request Transfer Sources and Destinations in Normal Mode
Transfer Direction (Settable Memory Interface)
Transfer Source
Transfer Destination
Usable
Address DMAC
Mode Channels
1 Synchronous DRAM
External device with DACK
Single 0, 1
2 External device with DACK
Synchronous DRAM
Single 0, 1
3 SRAM-type, DRAM
External device with DACK
Single 0, 1
4 External device with DACK
SRAM-type, DRAM
Single 0, 1
5 Synchronous DRAM
SRAM-type, MPX, PCMCIA * Dual
0, 1
6 SRAM-type, MPX, PCMCIA * Synchronous DRAM
Dual
0, 1
7 SRAM-type, DRAM, PCMCIA,
SRAM-type, MPX, PCMCIA * Dual
0, 1
MPX
8 SRAM-type, MPX, PCMCIA * SRAM-type, DRAM, PCMCIA,
Dual
0, 1
MPX
*: DACK output setting in dual address mode transfer
"SRAM-type" in the table indicates an SRAM, byte control SRAM, or burst ROM setting.
Notes: 1. Memory interfaces on which transfer is possible in single address mode are SRAM,
byte control SRAM, burst ROM, DRAM, and synchronous DRAM.
2. When performing dual address mode transfer, make the DACK output setting for the
SRAM, byte control SRAM, burst ROM, PCMCIA, or MPX interface.
(b) DDT Mode
Table 14.9 shows the memory interfaces that can be specified for the transfer source and transfer
destination in DMA transfer initiated by an external request supported by the SH7750 Series in
DDT mode.
Rev. 6.0, 07/02, page 525 of 986