HD6417750 Datasheet, PDF (306/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Table 10.4 FRQCR Settings and Internal Clock Frequencies
FRQCR
(Lower 9 Bits)
CPU Clock
Frequency Division Ratio
Bus Clock
Peripheral Module Clock
H'008
1
1/2
1/2
H'00A
1/4
H'00C
1/8
H'011
1/3
1/3
H'013
1/6
H'01A
1/4
1/4
H'01C
1/8
H'023
1/6
1/6
H'02C
1/8
1/8
H'05A
1/2
1/4
1/4
H'05C
1/8
H'063
1/6
1/6
H'06C
1/8
1/8
H'0A3
1/3
1/6
1/6
H'0EC
1/4
1/8
1/8
Note: For the lower 9 bits of FRQCR, do not set values other than those shown in the table.
10.4 CPG Register Description
10.4.1 Frequency Control Register (FRQCR)
The frequency control register (FRQCR) is a 16-bit readable/writable register that specifies
use/non-use of clock output from the CKIO pin, PLL circuit 1 and 2 on/off control, and the CPU
clock, bus clock, and peripheral module clock frequency division ratios. Only word access can be
used on FRQCR.
FRQCR is initialized only by a power-on reset via the 5(6(7 pin. The initial value of each bit is
determined by the clock operating mode.
Rev. 6.0, 07/02, page 254 of 986