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HD6417750 Datasheet, PDF (128/1039 Pages) Renesas Technology Corp – SuperH RISC engine | |||
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VA is
in P4 area
Data access to virtual address (VA)
VA is
in P2 area
VA is
in P1 area
VA is in P0, U0,
or P3 area
On-chip I/O access
No
0
CCR.OCE?
1
0
CCR.CB?
1
VPNs match
and V = 1
Yes
No MMUCR.AT = 1
Yes
CCR.WT?
0
No
1
SH = 0
and (MMUCR.SV = 0 or
SR.MD = 0)
Yes
No
VPNs match
and ASIDs match and
V=1
Yes
Data TLB miss
exception
00 or
01 W
PR?
10
R/W?
R
Data TLB protection
violation exception
Only one
No
entry matches
Yes
0 (User)
SR.MD?
1 (Privileged)
Data TLB multiple
hit exception
11
R/W? W
Memory access
01 or 11
00 or 10
W R/W?
R/W? W
R
1
R
D?
0
R
Data TLB protection
violation exception
Initial page write
exception
Cache access
in copy-back mode
C=1
No
and CCR.OCE = 1
Yes
0
WT?
1
Cache access
in write-through mode
Memory access
(Non-cacheable)
Figure 3.10 Flowchart of Memory Access Using UTLB
Rev. 6.0, 07/02, page 76 of 986
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