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| HD6417750 Datasheet, PDF (949/1039 Pages) Renesas Technology Corp – SuperH RISC engine | |||
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CKIO
BANK
TRs1
TRs2
TRs3
TRs4
tAD
Precharge-sel
Address
tCSD
tCSD
tCSD
tRWD
RD/
tRASD tRASD
tRASD
tCASD2
tCASD2
tCASD2
TRs5
Trc
Trc
Trc
tAD
tRWD
tCASD2
tCSD
tRASD
DQMn
D63âD0
(write)
CKE
DACKn
tDQMD
tWDD
tCKED
tDACD
tBSD
tCKED
tDQMD
tWDD
tDACD
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 22.35 Synchronous DRAM Bus Cycle: Synchronous DRAM Self-Refresh
(TRC[2:0] = 001)
Rev. 6.0, 07/02, page 897 of 986
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