HD6417750 Datasheet, PDF (368/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Table 13.1 BSC Pins (cont)
Name
Data enable 6
Signals
I/O
:(9/&$69/ O
DQM6
Data enable 7
:(:/&$6:/ O
DQM7/5(*
Ready
Area 0 MPX
interface
specification/
16-bit I/O
5'<
I
MD6/,2,649 I
Clock enable
Bus release
request
Bus use
permission
Area 0 bus
width/PCMCIA
card select
CKE
O
%5(4/
I
%6$&.
%$&./
O
%65(4
MD3/&(5$*¹ I/O
MD4/&(5%*²
Endian switchover/ MD5/5$65*³ I/O
row address strobe
Master/slave
MD7/TXD
I/O
switchover
DMAC0
DACK0
O
acknowledge
signal
DMAC1
DACK1
O
acknowledge
signal
Description
When setting synchronous DRAM interface:
selection signal for D55–D48
When setting DRAM interface: &$6 signal for
D55–D48
When setting MPX interface: high-level output
In other cases: write strobe signal for D55–D48
When setting synchronous DRAM interface:
selection signal for D63–D56
When setting DRAM interface: &$6 signal for
D63–D56
When setting PCMCIA interface: 5(* signal
When setting MPX interface: high-level output
In other cases: write strobe signal for D63–D56
Wait state request signal
In power-on reset: Designates area 0 bus as MPX
interface (1: SRAM, 0: MPX)
When setting PCMCIA interface: 16-bit I/O
designation signal. Valid only in little-endian mode.
Synchronous DRAM clock enable control signal
Bus release request signal/bus acknowledge signal
Bus use permission signal/bus request
In power-on reset*⁴: external space area 0 bus width
specification signal
When setting PCMCIA interface: &(5$, &(5%
Endian specification in a power-on reset.*⁴
5$65 when DRAM is connected to area 2
Indicates master/slave status in a power-on reset.*⁴
Serial interface TXD
DMAC channel 0 data acknowledge
DMAC channel 1 data acknowledge
Rev. 6.0, 07/02, page 316 of 986