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HD6417750 Datasheet, PDF (242/1039 Pages) Renesas Technology Corp – SuperH RISC engine | |||
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Table 7.10 Floating-Point Double-Precision Instructions
Instruction
FABS
DRn
FADD
DRm,DRn
FCMP/EQ DRm,DRn
FCMP/GT DRm,DRn
FDIV
FCNVDS
FCNVSD
FLOAT
FMUL
FNEG
DRm,DRn
DRm,FPUL
FPUL,DRn
FPUL,DRn
DRm,DRn
DRn
FSQRT
FSUB
FTRC
DRn
DRm,DRn
DRm,FPUL
Operation
Instruction Code
Privileged T Bit
DRn & H'7FFF FFFF FFFF
1111nnn001011101 â
â
FFFF â DRn
DRn + DRm â DRn
1111nnn0mmm00000 â
â
When DRn = DRm, 1 â T
Otherwise, 0 â T
1111nnn0mmm00100 â
Comparison
result
When DRn > DRm, 1 â T
Otherwise, 0 â T
1111nnn0mmm00101 â
Comparison
result
DRn /DRm â DRn
1111nnn0mmm00011 â
â
double_to_ float[DRm] â FPUL 1111mmm010111101 â
â
float_to_ double [FPUL] â DRn 1111nnn010101101 â
â
(float)FPUL â DRn
1111nnn000101101 â
â
DRn * DRm â DRn
1111nnn0mmm00010 â
â
DRn ^ H'8000 0000 0000 0000 1111nnn001001101 â
â
â DRn
DRn DRn
1111nnn001101101 â
â
DRn â DRm â DRn
1111nnn0mmm00001 â
â
(long) DRm â FPUL
1111mmm000111101 â
â
Table 7.11 Floating-Point Control Instructions
Instruction
LDS Rm,FPSCR
LDS Rm,FPUL
LDS.L @Rm+,FPSCR
LDS.L @Rm+,FPUL
STS FPSCR,Rn
STS FPUL,Rn
STS.L FPSCR,@-Rn
STS.L FPUL,@-Rn
Operation
Rm â FPSCR
Rm â FPUL
(Rm) â FPSCR, Rm+4 â Rm
(Rm) â FPUL, Rm+4 â Rm
FPSCR â Rn
FPUL â Rn
Rn â 4 â Rn, FPSCR â (Rn)
Rn â 4 â Rn, FPUL â (Rn)
Instruction Code
Privileged
0100mmmm01101010 â
0100mmmm01011010 â
0100mmmm01100110 â
0100mmmm01010110 â
0000nnnn01101010 â
0000nnnn01011010 â
0100nnnn01100010 â
0100nnnn01010010 â
T Bit
â
â
â
â
â
â
â
â
Rev. 6.0, 07/02, page 190 of 986
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