HD6417750 Datasheet, PDF (751/1039 Pages) Renesas Technology Corp – SuperH RISC engine

After the serial transmitter is initialized, the TxD2 pin function is not selected and the value of the
SPB2DT bit substitutes for the mark state until the TE bit is set to 1 (i.e. transmission is enabled).
The SPB2IO and SPB2DT bits should therefore be set to 1 (designating output and high level)
beforehand.
To send a break signal during serial transmission, clear the SPB2DT bit to 0 (designating low
level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the
transmitter is initialized, regardless of its current state, and 0 is output from the TxD2 pin.
Receive Data Sampling Timing and Receive Margin: The SCIF operates on a base clock with a
frequency of 16 times the transfer rate. In reception, the SCIF synchronizes internally with the fall
of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the
eighth base clock pulse. The timing is shown in figure 16.13.
16 clocks
8 clocks
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
Base clock
–7.5 clocks
+7.5 clocks
Receive data
(RxD2)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 16.13 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
M = (0.5 – ¹ ) – (L – 0.5) F – ^{| D – 0.5 |} (1 + F) × 100% ^{....................... (1)}
2N
N
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
Rev. 6.0, 07/02, page 699 of 986