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HD6417750 Datasheet, PDF (231/1039 Pages) Renesas Technology Corp – SuperH RISC engine | |||
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7.3 Instruction Set
Table 7.2 shows the notation used in the following SH instruction list.
Table 7.2 Notation Used in Instruction List
Item
Format
Description
Instruction
mnemonic
OP.Sz SRC, DEST
OP:
Sz:
SRC:
DEST:
Operation code
Size
Source
Source and/or destination operand
Summary of
operation
â, â: Transfer direction
(xx): Memory operand
M/Q/T: SR flag bits
&:
Logical AND of individual bits
|:
Logical OR of individual bits
â§:
Logical exclusive-OR of individual bits
~:
Logical NOT of individual bits
<<n, >>n: n-bit shift
Instruction code MSB â LSB
mmmm: Register number (Rm, FRm)
nnnn: Register number (Rn, FRn)
0000: R0, FR0
0001: R1, FR1
:
1111: R15, FR15
mmm: Register number (DRm, XDm, Rm_BANK)
nnn: Register number (DRm, XDm, Rn_BANK)
000: DR0, XD0, R0_BANK
001: DR2, XD2, R1_BANK
:
111: DR14, XD14, R7_BANK
mm: Register number (FVm)
nn:
Register number (FVn)
00:
FV0
01:
FV4
10:
FV8
11:
FV12
iiii:
Immediate data
dddd: Displacement
Privileged mode
âPrivilegedâ means the instruction can only be executed
in privileged mode.
T bit
Value of T bit after â: No change
instruction execution
Note: Scaling (Ã1, Ã2, Ã4, or Ã8) is executed according to the size of the instruction operand(s).
Rev. 6.0, 07/02, page 179 of 986
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