HD6417750 Datasheet, PDF (408/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 15: TRWL2
0
Bit 14: TRWL1
0
1
1
0
1
Note: * Inhibited in RAS down mode.
Bit 13: TRWL0
0
1
0
1
0
1
0
1
Write Precharge ACT Delay Time
1 (Initial value)
2
3*
4*
5*
Reserved (Setting prohibited)
Reserved (Setting prohibited)
Reserved (Setting prohibited)
Bits 12 to 10—CAS-Before-RAS Refresh 5$6 Assertion Period (TRAS2–TRAS0): When the
DRAM interface is set, these bits set the 5$6 assertion period in CAS-before-RAS refreshing.
When the synchronous DRAM interface is set, the bank active command is not issued for a period
of TRC* + TRAS after an auto-refresh command is issued.
Note: * Bits 29 to 27: RAS precharge interval at end of refresh.
Bit 12: TRAS2
0
Bit 11: TRAS1
0
Bit 10: TRAS0
0
5$6/DRAM
Assertion Period
2
1
3
1
0
4
1
5
1
0
0
6
1
7
1
0
8
1
9
Note: * Bits 29 to 27: RAS precharge interval at end of refresh.
Command
Interval after
Synchronous
DRAM Refresh
4 + TRC*
(Initial value)
5 + TRC
6 + TRC
7 + TRC
8 + TRC
9 + TRC
10 + TRC
11 + TRC
Bit 9—Burst Enable (BE): Specifies whether burst access is performed on DRAM interface. In
synchronous DRAM access, burst access is always performed regardless of the specification of
this bit. The DRAM transfer mode depends on EDOMODE.
Rev. 6.0, 07/02, page 356 of 986