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| HD6417750 Datasheet, PDF (931/1039 Pages) Renesas Technology Corp – SuperH RISC engine | |||
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CKIO
A25âA0
RD/
T1
Tw
Twe
T2
tAD
tCSD
tRWD
tRSD
tRSD
tAD
tCSD
tRWD
tRSD
D63âD0
(read)
tWED1
tWEDF
tRDS
tRDH
tWEDF
D63âD0
(write)
tWDD
tWDD
tBSD
tBSD
tWDD
tRDYS
tRDYH
DACKn
(SA: IO â memory)
tDACD
tRDYS
tDACD
DACKn
(SA: IO â memory)
tDACDF
DACKn
(DA)
tDACD
tRDYH
tDACD
tDACDF
tDACD
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 22.17 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait)
Rev. 6.0, 07/02, page 879 of 986
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