HD6417750 Datasheet, PDF (439/1039 Pages) Renesas Technology Corp – SuperH RISC engine

13.3.3 SRAM Interface
Basic Timing: The SRAM interface of the SH7750 Series uses strobe signal output in
consideration of the fact that mainly SRAM will be connected. Figure 13.6 shows the basic timing
of normal space accesses. A no-wait normal access is completed in two cycles. The %6 signal is
asserted for one cycle to indicate the start of a bus cycle. The &6Q signal is asserted on the T1
rising edge, and negated on the next T2 clock rising edge. Therefore, there is no negation period in
case of access at minimum pitch.
There is no access size specification when reading. The correct access address is output to the
address pins (A[25:0]), but since there is no access size specification, 32 bits are always read in
the case of a 32-bit device, and 16 bits in the case of a 16-bit device. When writing, only the :(
signal for the byte to be written is asserted. For details, see section 13.3.1, Endian/Access Size and
Data Alignment.
In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width.
The first access is performed on the data for which there was an access request, and the remaining
accesses are performed in wrap around mode on the data at the 32-byte boundary. The bus is not
released during this transfer.
Rev. 6.0, 07/02, page 387 of 986