HD6417750 Datasheet, PDF (980/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Table 22.36 Peripheral Module Signal Timing (3)
Module
TMU,
RTC
SCI
I/O
ports
Item
Symbol
Timer clock
pulse width
(high)
t
TCLKWH
Timer clock
pulse width
(low)
t
TCLKWL
Timer clock
t
TCLKr
rise time
Timer clock
t
TCLKf
fall time
Oscillation t
ROSC
settling time
Input clock t
Scyc
cycle (asyn-
chronous)
Input clock t
Scyc
cycle (syn-
chronous)
Input clock
t
SCKW
pulse width
Input clock t
SCKr
rise time
Input clock t
SCKf
fall time
Transfer data t
TXD
delay time
Receive data t
RXS
setup time
(synchronous)
Receive data t
RXH
hold time
(synchronous)
Output data
delay time
t
PORTD
Input data
setup time
t
PORTS
Input data
hold time
t
PORTH
HD6417750
VF128
*²
Min Max
4
—
4
—
— 0.8
— 0.8
—3
4
—
6
—
0.4 0.6
— 0.8
— 0.8
1.3 10
16 —
16 —
0.5 10
3.5 —
1.5 —
HD6417750
F167
HD6417750
F167I
*³
Min Max
4
—
4
—
— 0.8
— 0.8
—3
4
—
6
—
0.4 0.6
— 0.8
— 0.8
1.3 8
16 —
16 —
0.5 8
3.5 —
1.5 —
HD6417750
BP200M
*⁴
Min Max Unit Figure
4
— Pcyc*¹ 22.61
4
— Pcyc*¹ 22.61
— 0.8 Pcyc*¹ 22.61
— 0.8 Pcyc*¹ 22.61
—3
s
22.62
4
— Pcyc*¹ 22.63
6
— Pcyc*¹ 22.63
0.4 0.6 t
Scyc
22.63
— 0.8 Pcyc*¹ 22.63
— 0.8 Pcyc*¹ 22.63
1.2 6
ns
22.64
16 — ns
22.64
16 — ns
22.64
0.5 6
ns
3
— ns
1.5 — ns
22.65
22.65
22.65
Rev. 6.0, 07/02, page 928 of 986