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HD6417750 Datasheet, PDF (984/1039 Pages) Renesas Technology Corp – SuperH RISC engine
CKIO
DBREQ
BAVL
TR
tDBQS
tDBQH
tBAVD
tBAVD
tTRS
tTRH
D63 to D0
(READ)
tDTRS
tDTRH
(2)
(1)
(1): [2CKIO cycle – tDTRS] (= 18 ns: 100 MHz)
(2): DTR = 1CKIO cycle (= 10 ns: 100 MHz)
(tDTRS + tDTRH) < DTR < 10 ns
Figure 22.66(b) '%5(4/75 Input Timing and %$9/ Output Timing
tTCKH
tTCKcyc
tTCKL
VIH
VIH
1/2VDDQ
VIL
VIL
tTCKf
Note: When clock is input from TCK pin
Figure 22.67 TCK Input Timing
VIH
1/2VDDQ
tTCKr
(Low)
SCK2/
(High)
/
BRKACK
tASEBRKS tASEBRKH
tASEBRKS tASEBRKH
Figure 22.68 5(6(7 Hold Timing
Rev. 6.0, 07/02, page 932 of 986